1. Field of the Invention
The present invention relates to hard disk drives. More particularly, the present invention relates to an embedded servo hard disk drive providing fault-tolerant, synchronous sync mark detection.
2. Description of the Prior Art and Related Information
A huge market exists for hard disk drives for mass-market host computer systems such as servers, desktop computers, and laptop computers. To be competitive in this market, a hard disk drive must be relatively inexpensive, and must accordingly embody a design that is adapted for low-cost mass production. In addition, it must provide substantial capacity, rapid access to data, and reliable performance. Numerous manufacturers compete in this huge market and collectively conduct substantial research and development, at great annual cost, to design and develop innovative hard disk drives to meet increasingly demanding customer requirements.
Each of numerous contemporary mass-market hard disk drive models provides relatively large capacity, often in excess of 1 gigabyte per drive. Nevertheless, there exists substantial competitive pressure to develop mass-market hard disk drives having even higher capacities. Another requirement to be competitive in this market is that the hard disk drive must conform to a selected standard exterior size and shape often referred to as a xe2x80x9cform factor.xe2x80x9d Generally, capacity is desirably increased without increasing the form factor or the form factor is reduced without decreasing capacity.
Satisfying these competing constraints of low-cost, small size, and high capacity requires a design that provides high format efficiency and high areal storage density. Format efficiency relates to the percentage of available area that is available for storing user data rather than being consumed by control data, gaps, etc. Areal storage density relates to the amount of data storage capacity per unit of area on the recording surfaces of the disks. The available areal density may be determined from the product of the track density measured radially and the linear bit density measured along the tracks.
The available track density depends on numerous factors including the performance capability of a servo system in the hard disk drive which, among other things, provides for track following, i.e., maintaining alignment of a reading or writing transducer with respect to the centerline of a desired track. One type of servo system, sometimes referred to as an xe2x80x9cembedded servoxe2x80x9d employs servo data on the same disk surface that stores user data to provide signals employed in the operation of the servo system. An embedded servo format for the disk surface has the basic characteristic of a plurality of radially-extending servo-data regions (sometimes referred to as xe2x80x9cservo wedgesxe2x80x9d) and an interspersed plurality of radially-extending user-data regions. Each user-data region has a plurality of user-data track segments, and each servo-data region has a plurality of servo-data track segments. In accord with another element of an embedded servo format, the servo data include track-identification data used during track-seeking operations, and- burst data used during track-following operations. While data are being read in operation of an embedded servo hard disk drive, a transducer produces a time-multiplexed analog read signal that during a revolution of the disk represents servo data during each of a first set of time intervals; and represents user data during each of a second set of time intervals.
The rate at which servo wedges pass under a reading transducer is referred to as the xe2x80x9cservo sample rate.xe2x80x9d The servo sample rate equals the revolution rate of the rotating disk multiplied by the number of servo wedges per surface. A high servo sample rate is desirable for the purpose of providing a robust servo system. On the other hand, increasing the servo sample rate generally involves allocating more surface area to servo wedges and thereby adversely impacts surface format efficiency.
The available linear bit density depends on numerous factors including the performance capability of certain circuitry that is commonly referred to as a xe2x80x9cread channel.xe2x80x9d One type of read channel is referred to as a peak-detecting channel; another type is referred to as a sampled-data channel. The type referred to as a sampled-data channel is a category including a partial response, maximum likelihood (xe2x80x9cPRMLxe2x80x9d) channel, a EPR4 channel, and a E2PR4 channel.
In a hard disk drive having any of these read channels, the read channel receives an analog read signal from a transducer during a read operation. The analog read signal is characterized by a xe2x80x9cchannel frequency.xe2x80x9d As used in this art, xe2x80x9cchannel frequencyxe2x80x9d is the reciprocal of a time period xe2x80x9cT,xe2x80x9d where the xe2x80x9cTxe2x80x9d is the time period consumed while an elemental-length magnet passes under the transducer during a read operation with the disk spinning at a constant angular velocity. In this regard, the length of each magnet recorded along a track as a result of a write operation is, to a first order of approximation, either an elemental length or an integer multiple of the elemental length. Each elemental length magnet can be referred to as a xe2x80x9cbit cellxe2x80x9d that is defined during a write operation.
The analog read signal always contains some random noise. The analog read signal, and certain other signals produced by processing the analog read signal and that also contain noise, are referred to herein as noise-corrupted signals. One such other noise-corrupted signal is a signal produced by filtering the analog read signal by means of a low-pass filter. Such filtering may reduce but not eliminate noise, and the filtered signal is also noise corrupted. Further signal processing in the read channel provides for producing a digital signal comprising detected symbols, any of which can be in error in representing recovered data. Such a digital signal is referred to herein as an error-prone signal.
In a hard disk drive employing a peak detecting channel, digital data are represented in the media by transitions between oppositely magnetized bit cells. Provided that the transitions between oppositely magnetized bit cells do not unduly interfere with each other, each such transition causes a peak in the analog read signal, and a peak-detecting channel employs a peak detector that detects such peaks, and produces digital signal in the form of a serial, binary-valued signal that is an error-prone signal for numerous reasons. One reason why the peak detector produces an error-prone signal is random noise; this source of error presents a problem for any type of channel. Another reason relates to interference between adjacent transitions. Interference between such transitions is referred to as intersymbol interference and adversely affects performance of a peak detetecting channel increasingly as a function of channel rate.
A sampled-data channel employs sampling circuitry that samples a noise-corrupted analog read signal to produce a sequence of noise-corrupted samples. The samples so produced are provided in sequence to a detector such as a so-called xe2x80x98Viterbi detectorxe2x80x9d that internally produces error-prone symbols and maps the internally-produced error-prone symbols; to binary-valued error-prone symbols. In a PRML channel, such internally-produced error-prone symbols are often referred to as: xe2x80x9cxe2x88x921xe2x80x9d; xe2x80x9c0xe2x80x9d; and xe2x80x9c+1xe2x80x9d; and the binary-valued error-prone symbols are supplied to a deserializer to produce a parallel-by-bit digital signal.
A single binary digit (bit) has only two possible values and, accordingly, by itself can represent very little information. A plurality of bits can be grouped in a predetermined order to represent much more information. As one representative example, four bits can be grouped in a most-significant-bit to least-significant-bit order to provide for representing any one of the sixteen hexidecimal digits xe2x80x9c0xe2x80x9d to xe2x80x9cF.xe2x80x9d
Such a four-bit grouping is often referred to as a xe2x80x9cnibblexe2x80x9d; an eight-bit grouping is commonly referred to as a xe2x80x9cbyte.xe2x80x9d Groups of 4-bits bytes or 8-bit bytes are very commonly used as elements, in a hierarchical grouping of bits, to provide for representing an even larger amount of information.
In processing information, it is necessary to ensure consistency in the ordering of bits composing a block of bits. One common approach directed to ensuring such consistency employs multiple stored fields including a PLL field to facilitate bit synchronization and a sync field to facilitate block synchronization. The sync field facilitates block synchronization by holding a special marker that is detected to xe2x80x9cframexe2x80x9d data, i.e., to identify a boundary of a block.
U.S. Pat. No. 4,914,535 to Weng (the ""535 patent) relates to identifying the location of data bits in a disk drive that may involve a dedicated servo and a peak detection channel, there being no teaching in the ""535 patent of either an embedded servo or a sampled-data channel. The ""535 patent teaches employing a special manufacturing apparatus (a synchronization sequence generator) to record, during manufacture, a special synchronization sequence to assist in identifying the location of the start of bits in a given sector. The special synchronization sequence is selected to maximize the minimum Hamming distance between the symbol sequence and any shifted version of the the symbol sequence which has been shifted to the left by one or more bits, where the Hamming distance is the number of symbol positions in which the two symbol sequence differ.
In contemporary hard disk drives employing embedded servos, it is well known to provide framing of servo data via a servo sync mark and to provide framing of user data via a data sync mark.
Certain prior art embedded-servo hard disk drives employ a peak detecting channel for recovering servo data and a PRML channel for recovering user data. Certain such prior art drives implement the PRML channel for user data in a commercially available integrated circuit referred to as Model No. 4904 obtained from Silicon Systems, Inc. (the xe2x80x9cSSi 4904xe2x80x9d). In such drives incorporating the SSi 4904, every write operation involves writing an AGC/PLL field, then a data sync mark, then the user data. Each bit to be written is processed through a xe2x80x9cprecodexe2x80x9d operation and then stored in the form of bit cells each of which can be represented either as axe2x80x9c+xe2x80x9d or a xe2x80x9cxe2x88x92xe2x80x9d bit cell. The AGC/PLL bits are all xe2x80x9c1xe2x80x9d and, after preceding, are written to form a repeating string of bit cells xe2x80x9c++xe2x88x92xe2x88x92++xe2x88x92xe2x88x92xe2x80x9d; the expected binary-valued symbols produced during a read operation are all xe2x80x9c1.xe2x80x9d The data sync mark to be written can be represented by of the following pattern (where the bit positions are numbered to indicate time order during a write operation, e.g., xe2x80x9c0xe2x80x9d being the first written of the group and xe2x80x9c8xe2x80x9d being the last written of the group):
This pattern can be described as hex 0D9, where the least significant digit xe2x80x9c9xe2x80x9d corresponds to write bit positions 5-8, the next most significant digit xe2x80x9cDxe2x80x9d corresponds to write bit positions 1-4, and the most significant digit xe2x80x9c0xe2x80x9d corresponds to write bit position 0.
This sync mark, after precoding and as stored in the bit cells, can be represented as:
Cell magnets: xe2x88x92 + + + xe2x88x92 xe2x88x92 xe2x88x92 xe2x88x92 +
During a read operation, the AGC/PLL field facilitates providing for bit synchronization, and the data sync mark facilitates providing for block synchronization. However, noise influences can cause bit-detection errors; furthermore there is a risk of a pattern-detect error; i.e., that a nonmark substring will be misdetected as a sync mark. There will now be set forth several rows of information to provide examples involving several possible patterns. The first row (xe2x80x9cBit positionsxe2x80x9d) is a heading for each of the other rows and identifies bit positions as being numbered from xe2x80x9cxe2x88x9211xe2x80x9d to xe2x80x9c00.xe2x80x9d The second row (xe2x80x9cSync word patternxe2x80x9d) sets forth a nine-symbol long string (extending from bit position xe2x80x9cxe2x88x9208xe2x80x9d to bit position xe2x80x9c00xe2x80x9d) for the above-described sync mark (hex 0D9). The third row (xe2x80x9cCorrect match examplexe2x80x9d) sets forth an example of operation in which the correct sync word occupies the correct bit positions xe2x80x9cxe2x88x9208xe2x80x9d through xe2x80x9c00xe2x80x9d within a twelve-symbol long string. The fourth row (xe2x80x9cBit error positionsxe2x80x9d) concerns an example of Operation in which errors cause a pattern misdetection (an early one), and identifies with an xe2x80x9cexe2x80x9d each of two bit positions in which a bit misdetect error occurs in this example. The fifth row: (xe2x80x9cMisdetect examplexe2x80x9d) shows that the two bit misdetect errors in positions xe2x80x9cxe2x88x9211xe2x80x9d and xe2x80x9cxe2x88x9204xe2x80x9d result in an early pattern misdetection.
In the foregoing Misdetect example, there are only 2 symbols in error, viz., one in bit position xe2x80x9cxe2x88x9211xe2x80x9d and the other in bit position xe2x80x9cxe2x88x9204.xe2x80x9d Even though only two symbols are in error, the 9-symbol detected string starting at bit position xe2x80x9cxe2x88x9211xe2x80x9d will be misdetected as a data sync mark. Such pattern misdetection causes all the following user data to be misinterpreted.
The foregoing example involves a data sync mark with only 9 bits. A prior art patent, viz., U.S. Pat. No. 5,384,671 (the ""671 patent) proposes a servo sync mark comprising 19 bits. In particular, the ""671 patent in its columns 7 and 8 describes an AGC/PLL field followed by the particular 19-bit servo sync mark followed by a gray code for track ID. The ""671 patent states that the particular 19-bit servo sync mark xe2x80x9cis selected to have a minimum correlation (maximum Hamming distance) relative to the AGC/PLL 1/4 T pattern, and also to the Gray coded pattern coding convention (irrespective of the actual values included within the Gray coded pattern).xe2x80x9d
There will now be set forth several rows of information to provide examples involving the particular 19-bit servo sync mark the ""671 patent teaches. The first row (xe2x80x9cBit positionsxe2x80x9d) is a heading for each of the other rows and identifies bit positions as being numbered from xe2x80x9cxe2x88x9220xe2x80x9d to xe2x80x9c00.xe2x80x9d The second row (xe2x80x9cSWPxe2x80x9dxe2x80x94i.e., Sync Word Pattern) sets forth the nineteen-symbol long string (extending from bit position xe2x80x9cxe2x88x9218xe2x80x9d to bit position xe2x80x9c00xe2x80x9d) for this particular 19-bit servo sync mark. The third row (xe2x80x9cCMExe2x80x9dxe2x80x94i.e., Correct Match Example) sets forth an example of operation in which the correct sync word occupies the correct bit positions xe2x80x9cxe2x88x9218xe2x80x9dthrough xe2x80x9c00xe2x80x9d within a twenty-one-symbol long string. The fourth row (xe2x80x9cBEPxe2x80x9dxe2x80x94i.e., Bit Error Position) concerns an example of operation in which bit-detection errors cause a pattern misdetection (an early one), and identifies with an xe2x80x9cexe2x80x9d each of six bit positions in which a bit misdetect error occurs in this example. The fifth row (xe2x80x9cMExe2x80x9dxe2x80x94i.e., Misdetect example) shows that the six bit misdetect errors in positions result in an early pattern misdetection.
In this example, there are only six symbols in error, viz., those in bit positions:xe2x80x9cxe2x88x9219xe2x80x9d, xe2x80x9cxe2x88x9215xe2x80x9d; xe2x80x9cxe2x88x9213xe2x80x9d; xe2x80x9cxe2x88x9210xe2x80x9d; xe2x80x9cxe2x88x9208xe2x80x9d; and xe2x80x9cxe2x88x9202xe2x80x9d; however, the 19-symbol detected substring starting at position xe2x80x9cxe2x88x9220xe2x80x9d will be misdetected as a servo sync mark. Even though 19 symbols are consumed by every servo sync mark (and therefore adversely affecting format efficiency compared with the prior example), misdetection of a nonmark string remains reasonably probable in a high channel frequency read channel.
The foregoing demonstrates that a need exists in the hard disk drive art to provide for fault-tolerant synchronous sync mark detection of a sync mark substring of a concatenated string of error-prone read symbols and for providing a reduced risk that a nonmark substring of the concatenated string of error-prone read symbols will be misdetected as a sync mark.
This invention can be regarded as a hard disk drive having a pattern detector for providing fault-tolerant detection of a data sync mark represented by a substring of a concatenated string of error-prone read symbols and for providing a reduced risk of detection error such as having a nonmark substring of the concatenated string of error-prone read symbols being misdetected as a sync mark. The drive comprises a disk having a plurality of track segments; write means having an input for receiving bits; and means operative during a first operation for supplying a sequence of write bits that are received at the input of the write means.
The sequence of write bits define a preamble write string, a data sync mark write string, and a user data write string. The preamble write string and the data sync mark write string correspond to a concatenated string of expected symbols. The write means has means responsive to each write bit received at the input of the write means for magnetically defining a respective bit cell of a sequence of bit cells along a track segment.
The drive further comprises a sampled-data read channel including read means operative during a second operation for responding to the sequence of bit cells defined during the first operation to produce a sequence of error-prone read symbols that are subject to error in duplicating the concatenated string of expected symbols. Preferably, the read means includes sampling circuitry, timing recovery circuitry, and symbol detection circuitry. The timing recovery circuitry cooperates with the sampling circuitry to achieve bit synchronization during an early phase of the second operation. A suitable symbol detector is defined in a Viterbi detector, and in a preferred embodiment the output of the Viterbi detector is supplied to the pattern detector.
In accord with a distinctive feature of the invention, the data sync mark write string corresponds to an ordered set of m expected symbols selected to have maximum distance from all non-mark substrings of m consecutive expected symbols that exist in the concatenated string of expected symbols. Selecting the data sync mark in this way has important advantages. The above-described prior art approach for selecting a servo sync mark involves correlating each candidate sync mark against not only the preamble substring but also the substrings that follow the sync mark. This approach results in the rejection of candidates that are more robust than candidates deemed acceptable under this prior art approach.
The drive further comprises means for enabling the pattern detector during an enabling interval within the second operation beginning after the read means has produced a portion of the sequence of noise-influenced read symbols; and the pattern detector includes fault-tolerant means operative during the enabling interval for producing a sync mark detection signal. Preferably the enabling means includes means for providing a control signal such as a control signal in a set of control signals referred to herein as xe2x80x9cRGATE.xe2x80x9d Preferably, the pattern detector includes register means through which error-prone symbols propagate on a first-in, first-out basis, and comparator circuitry that produces a sync detection signal when at least a predetermined number of the symbols in the register means match the expected data sync mark.
The foregoing and other features of the invention are described in detail below and set forth in the appended claims.